Semiconductor Engineering

Creating An Accurate FEOL CMP Model

For decades, semiconductor manufacturers have used chemical-mechanical polishing (CMP) as the primary technique for the smoothing and leveling (planarization) of dielectrics and metal layers. CMP ...
EDN

New CMP process for sub-100nm copper and low-k wafers

ACM Research, a two-year-old Californian company, says it can see the end of the road for chemical mechanical polishing (CMP), and is looking to move in on the market with a non-contact process. It ...
Semiconductor Engineering

Reducing Rework In CMP: An Enhanced Machine Learning-Based Hybrid Metrology Approach

The semiconductor industry is constantly marching toward thinner films and complex geometries with smaller dimensions, as well as newer materials. The number of chemical mechanical planarization (CMP) ...
EDN

Applied drives CMP process control down to 45 nm and smaller

To allow real-time control of dielectric chemical mechanical planarization (CMP) processes to the 45 nm device node and beyond, Santa Clara, Calif.-based semiconductor manufacturing equipment leader ...
AZOM

Using White Light Interferometry to Characterize CMP Processes

Electronic and computer processors with a higher speed need smaller features for integrated circuits (IC), which also need smoother and smaller substrate surfaces. Chemical mechanical polishing (CMP) ...
Portland Press Herald

CMP executive: Electric utility is committed to a transparent auditing process

Though a recent editorial said otherwise, the truth is that all three independent analyses of CMP's billing system were thorough and meticulous. An error has occurred ...